Delta-sigma (ΔΣ) analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are widely used for high-fidelity conversion of analog signals into digital form and vice versa. Single-bit ΔΣ ADCs and DACs are known to have a high degree of linearity owing to the inherent linearity of a single-bit DAC. On the other hand multi-bit ΔΣ ADCs and DACs are capable of greater resolution and/or bandwidth than their single-bit counterparts. In order to address the problem of linearity in a multi-bit DAC, mismatch-shaping is often used to attenuate the mismatch-induced errors of the DAC in the frequency bands of interest. Various forms of mismatch-shaping have been proposed, but in the context of a ΔΣ ADC all these schemes limit the maximum clock rate of the ADC. It would be desirable to have an ADC architecture which provides mismatch-shaping of arbitrary order and shape, while also removing the speed limitation of other schemes. In one conventional approach a ΔΣ ADC with mismatch-shaping includes, an element selection logic (ESL) block that converts the output of the internal ADC into unary-coded data consisting of M 1-bit digital signals which drive the feedback DAC. The purpose of the ESL block is to ensure that mismatch in the feedback DAC results in shaped noise. Unfortunately, the selection, or shuffling, operation increases the interval of time between when quantization is complete and when feedback can be applied to the loop filter, and this delay limits the clock frequency of the system. In another approach dynamically re-ordering the reference levels in the internal flash ADC such that it produces shuffled unary-coded data helps somewhat, but it is now the settling time of the reference levels which restricts the minimum clock period. The shuffle-code generator can be implemented entirely in digital form using hardware which mimics the element selection logic, or it can make use of analog hardware which essentially contains M 1-bit ΔΣ modulators.
Both of these approaches of mismatch-shaping restrict the clock period. In the case where shuffling is performed by digital circuitry in the feedback path, the delay of the shuffler plus the time allocated for quantization and DAC setup equals the minimum clock period. If shuffling of the reference levels is used, the minimum clock period equals the settling time of the shuffler (including the time needed for computing the new shuffling code) plus the time allocated for quantization. Furthermore, when digital logic is used to determine the shuffling code, only simple shaping schemes (such as first-order lowpass and its N-path derivatives) are convenient to implement. Using analog ΔΣ modulators to supply the shuffle code in reference-level shuffling removes this restriction, but requires the use of extra analog circuitry which does not aid in the shaping of quantization noise. In yet another approach shaping results are achieved with 1-bit feedback applied to a split and replicated front end. In addition to having the disadvantage of 1-bit feedback to the critical first stage, this arrangement requires a lot of routing and does not support arbitrary shaping.